About Company:
Respect. For you. For us. Your communities and the world community. At Maxim, we know that our actions impact the world around us…and we want that. It's our responsibility to respect the world where we all live and work. But there's more to this story. We must ensure that our impact is a positive one.
So in a practical world, the real story is about behavior. Our Code of Corporate Social Responsibility (PDF, 215kB) is our voice. It frames our social and environmental responsibility, our code of behavior. But we also know that our reputation does not just stop with us. We expect and require the same behavior from our supplier partners.
Job Role: Senior Design
Verification Engineer
Job Code: 1962
Location: Bangalore, n/a IN
Job Level: Experienced 10+ yrs exp (Non-Manager)
Education: Master's Degree
Category: Semiconductor
Job Description:
- Understanding the expected design functionality,
- Developing verification-plans and
- Implement verification infrastructure based on cutting edge methodologies and tools.
- Verification component development
- Methodology support
- Operation and maintenance
- Pre-and post-silicon verification & debug to achieve verification goals.
- Must be a good team player and have the ability to handle all verification implementation tasks independently in a multi-disciplinary team environment. Must have a good understanding of advanced verification methodologies – Metrics & Plan Driven Verification and have hands-on experience with: UVM/OVM/eRM.
Requirements:
- MSEE or MSCE with 10+ years of directly related industry experience in ASIC/SoC Verification
- Expert knowledge of Object Oriented Programming – System Verilog/SystemC, or Aspect Oriented Programming (e/Specman)
- Hands on experience and expert-level knowledge of advanced verification HVL based methodologies (UVM/OVM/eRM)
- Expert level knowledge of Coverage Driven Verification – Coverage Model design & implementation using HVLs (System Verilog/SyetemC/e)
- Verification Planning
- Assertion based checks (PSL/SVA)
- Team-player: ability to forge and maintain relationships with peer-organizations
- Simulation & debug
- Gate-level bring up
- Scripting: Perl/Ruby/Tcl
- Good communications skills
Additional Skills:
- Experience with Mixed Signal verification
- Modeling of analog (Real Number Models)
- Low Power Verification
- Formal Verification
- Experience with Cadence based Verification tools: IUS, EManager, IFV, Conformal
- TLM
- Experience leading verification teams
- Maxim is an EEO/AA Employer
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