Qualcomm hires Graphics Hardware Executives-San Diego


Qualcomm hires Graphics Hardware Executives-San DiegoAnnouncement:

Qualcomm uses a centralized recruiting process designed to allow applicants to be reviewed by multiple hiring managers and departments by applying to a single posting.  If you are involved in any part of the Graphics and Multimedia Hardware, you should apply to this posting.  
Qualcomm's Graphics Hardware Team is responsible for the digital and mixed-signal circuits and systems that are integrated into integrated circuits(ICs), SystemOnChip (SoCs) and complete chipsets that power Qualcomm’s wireless device portfolio.  The team is currently seeking candidates across a broad range of technologies, listed below, and part of the application process is a brief questionnaire that will allow you to communicate your particular interests to Qualcomm’s technical recruiters who review each applicant.  

 Requisition ID: T1907386

Job Title: Qualcomm Graphics Hardware Executives

Location: San Diego

Company Division: Qualcomm Technologies, Inc. - CDMA Technology 

Job Area: Engineering - Hardware 

Location: California - San Diego 

Required: Bachelor's, Computer and/or Electrical Engineering 

Preferred: Master's, Computer and/or Electrical Engineering 

Skills:

  • DFT/DFY/DFM/DFD strategies and implementation
  • RTL linting using Spyglass or other tools
  • RTL synthesis using Synopsys Design Compiler (DC) or DCT/DCG
  • Power analysis and reduction using Power Artist, Primetime-PX, Conformal LP, etc.
  • Logic equivalence checking using Conformal LEC or Formality for RTL-netlist and netlist-netlist checks
  • Static Timing Analysis, including constraints, exceptions and timing closure
  • Generation of netlist ECOs (with manual or automated methods) for functional and timing fixes
  • Generation of test vectors for evaluation and production test programs on ATE
  • Post-silicon support for SW/customer issues, debugging, RMAs, yield enhancement, etc.
  • Physical Design (Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Timing Closure)
  • Low Power (clock gating, power gating, power grids, power integrity)
  • Design Automation (CAD/EDA/Automation)
  • Methodology (Design Methodology, Simulation Tools, Performance Modeling)



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